It can be appreciated that several trends presently exist in the electronics industry. Devices are continually getting smaller, faster and require less power, while simultaneously being able to support and perform a greater number of increasingly complex and sophisticated functions. One reason for these trends is an ever increasing demand for small, portable and multifunctional electronic devices. For example, cellular phones, personal computing devices, and personal sound systems are devices which are in great demand in the consumer market. These devices rely on one or more small batteries as a power source and also require an ever increasing computational speed and storage capacity to store and process data, such as digital audio, digital video, contact information, database data and the like.
Accordingly, there is a continuing trend in the semiconductor industry to manufacture integrated circuits (ICs) with higher device densities. To achieve such high densities, there has been and continues to be efforts toward scaling down dimensions (e.g., at submicron levels) on semiconductor wafers. In order to accomplish such high densities, smaller feature sizes, smaller separations between features and layers, and/or more precise feature shapes are required, such as metal interconnects or leads, for example. The scaling-down of integrated circuit dimensions can facilitate faster circuit performance and/or switching speeds, and can lead to higher effective yield in IC fabrication processes by providing more circuits on a semiconductor die and/or more die per semiconductor wafer, for example,—where this also satisfies or furthers ongoing desires to streamline fabrication processes, enhance efficiency and/or reduce costs.
By way of example, high precision analog integrated circuits (IC's), such as analog-to-digital and digital-to-analog converters, for example, often require a number of capacitors for proper operation. Some of the capacitor requirements in a true eighteen bit converter IC, for example, are a ratio stability of less than 0.00075% over 10 years, a voltage coefficient of less than 10 ppm per volt, a temperature drift match of less than 0.05% per degree Celsius, dielectric absorption of less than 0.00075% and capacitance greater than 0.5 fF per square micrometer, among other things.
Such integrated circuit capacitors are generally formed as part of the IC fabrication process whereby a thin dielectric layer is established between two conductive plates. However, conventional IC fabrication techniques, such as patterning and/or etching, for example, have limitations as to the size and/or accuracy to which features can be produced thereby. It would, therefore, be desirable to be able to form one or more integrated circuit capacitors in a cost effective manner that allows smaller feature sizes to be more accurately produced without complicating the fabrication process so that device scaling can be furthered.